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74FR74 * 74FR1074 Dual D-Type Flip-Flop
March 1992 Revised August 1999
74FR74 * 74FR1074 Dual D-Type Flip-Flop
General Description
The 74FR74 and 74FR1074 are dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is transferred to the outputs on the rising edge of the clock input (CPn). The 74FR1074 is the negative edge triggered version of this device. Both parts feature asynchronous clear (CDn) and set (SDn) inputs which are low level enabled.
Features
s 74FR74 is pin-for-pin compatible with the 74F74 s True 150 MHz fMAX capability on 74FR74 s Outputs sink 24 mA and source 24 mA s Guaranteed pin-to-pin skew specifications
Ordering Code:
Order Number 74FR74SC 74FR74PC 74FR1074SC 74FR1074PC Package Number M14A N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
74FR74 74FR1074
(c) 1999 Fairchild Semiconductor Corporation
DS010977
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74FR74 * 74FR1074
Logic Symbols
74FR74
Pin Descriptions
Pin Names Dn CPn SDn CDn Qn Qn Data Inputs Clock Inputs Asynchronous Set Inputs Asynchronous Clear Inputs True Output Complementary Output Description
Truth Tables
74FR74 Inputs SD L H L H H H 74FR1074 CD H L L H H H CP X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0

X L
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Rising Edge Q0 = Previous Q(Q) before LOW-to-HIGH Clock Transition
74FR1074 Inputs SD L H L H H H CD H L L H H H CP X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0

X L
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Falling Edge Q0 = Previous Q(Q) before HIGH-to-LOW Clock Transition
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74FR74 * 74FR1074
Logic Diagrams
74FR74
74FR1074
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74FR74 * 74FR1074
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 2000V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage VOL IIH IBVI IIL VID IOD IOS ICEX ICC Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Circuit Leakage Test Output Short-Circuit Current Output HIGH Leakage Current Power Supply Current 24 mA Max -100 -275 50 mA A Max Max 4.75 3.75 2.5 2.4 2.0 0.5 5 7 -150 -1.8 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V V A A A mA V V Min Min Min Min Min Max Max Max Max 0.0 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -24 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VIN = 0.5V (Dn, CPn) VIN = 0.5V (CDn, SDn) IID = 1.9 A, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded VOUT = 0.0V VOUT = VCC
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74FR74 * 74FR1074
AC Electrical Characteristics 74FR74
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tOSHL (Note 3) tOSLH (Note 3) tOST (Note 3) tQ/Q (Note 3) tPS (Note 3) Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Pin to Pin Skew for HL Transitions Pin to Pin Skew for LH Transitions Pin to Pin Skew for HL/LH Transitions True/Complement Output Skew Pin (Signal) Transition Variation 150 2.5 2.5 1.5 2.0 VCC = +5.0V CL = 50 pF Typ 190 3.5 4.5 3.5 5.5 5.0 6.0 5.5 7.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 150 2.5 2.5 1.5 2.0 5.0 6.0 5.5 7.0 1.0 1.0 3.0 Max MHz ns Units
ns ns ns ns
1.8 1.8
ns ns
Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOST is guaranteed by design.
AC Operating Requirements 74FR74
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) (Note 4) tW(L) tREC SDn or CDn Pulse Width Recovery Time SDn or CDn to CPn
Note 4: This specification is guaranteed by design.
TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 2.5 2.5 0 0 3.3 3.3 Max ns ns ns Units
Max
Setup Time, HIGH or LOW Dn to CPn Hold Time, HIGH or LOW Dn to CPn CPn Pulse Width HIGH or LOW
2.5 2.5 0 0 3.3 3.3
4.0 2.0
4.0 2.0
ns ns
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74FR74 * 74FR1074
AC Electrical Characteristics 74FR1074
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tOSHL (Note 5) tOSLH (Note 5) tOST (Note 5) tQ/Q (Note 5) tPS (Note 5) Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Pin to Pin Skew for HL Transitions Pin to Pin Skew for LH Transitions Pin to Pin Skew for HL/LH Transitions True/Complement Output Skew Pin (Signal) Transition Variation 120 2.5 3.0 1.5 2.0 VCC = +5.0V CL = 50 pF Typ 160 4.0 5.0 3.5 5.5 5.5 6.5 5.5 7.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 120 2.5 3.0 1.5 2.0 5.5 6.5 5.5 7.0 1.5 1.5 3.5 Max MHz ns Units
ns ns ns ns
2.0 2.0
ns ns
Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOST is guaranteed by design.
AC Operating Requirements 74FR1074
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) (Note 6) tW(L) tREC SDn or CDn Pulse Width Recovery Time SDn or CDn to CPn
Note 6: This specification is guaranteed by design.
TA = 0C = +70C VCC = +5.0V CL = 50 pF Min 2.0 2.0 0 0 3.3 3.3 Max ns ns Units
Max
Setup Time, HIGH or LOW Dn to CPn Hold Time, HIGH or LOW Dn to CPn CPn Pulse Width HIGH or LOW
2.0 2.0 0 0 3.3 3.3
ns
4.0 2.0
4.0 2.0
ns ns
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74FR74 * 74FR1074
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
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74FR74 * 74FR1074 Dual D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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